The present invention relates generally to a semiconductor integrated circuit (IC) device, and more particularly, to a semiconductor integrated circuit device having a data bus inversion (DBI) function.
FIG. 1 is a block diagram showing a semiconductor integrated circuit (IC) device having a data bus inversion function according to the prior art.
Elements that relate to controlling performance of semiconductor IC devices for storing data are the central processing units (CPU) and/or graphic processing units (GPU). That is, the main memory devices or the graphic memory devices, wherein the data processing speed is one of the most important factors for these devices.
There are various technologies used to improve this data processing speed. One of these technologies currently being used is the data bus inversion (DBI).
For example, according to the data bus inversion function, if the number of data having a high value or a low value is four or more of eight data, current eight data is inverted and transmitted, and if the number of data having a high value or low value is less than four, the current eight data is transmitted without being inverted, wherein the data processing speed is improved by minimizing the number of times the eight data is switched prior to being outputted.
FIG. 1 shows a semiconductor integrated circuit 1 that has a data bus inversion function according to the prior art having a DBI flag generating unit 2, a first to eighth data output units 3 to 10, and a first to eighth pads 11 to 18.
The DBI flag generating unit 2 performs an operation on all of data ‘GIO<0:7><0:3>’ output from global transmission lines in a memory cell area, and generates DBI flag signals ‘DFLAG<0:3>’ to define whether data is inverted or not.
The first to eighth data output units 3 to 10 inverts data ‘GIO0<0:3>’ to ‘GIO7<0:3>’, which are respectively input to the first to eighth data output units 3 to 10, in accordance with the DBI flag signals ‘DFLAG<0:3>’, performs delay, multiplexing, and pipe latching processes on the data, and outputs the data to the respective first to eighth pads 11 to 18. On the layout area of the IC, these respective first to eighth data output units 3 to 10 are disposed. Also, in this same layout area of the IC, the data input circuits (not shown) are also disposed.
FIG. 2 shows a block diagram of a first data output unit with the device according to the prior art.
FIG. 2 shows each of the first to eighth data output units 3 to 10 of the prior art having the same structure. As shown in FIG. 2 of the prior art, the first data output unit 3 has a control/delay circuit unit 3-1, an inversion circuit unit 3-2, and a MULTIPLEXING/PIPE LATCH unit 3-3.
The control/delay circuit unit 3-1 and the inversion circuit unit 3-2 delays the data ‘GIO0<0:3>’ to match the timing of the data ‘GIO0<0:3>’ and the timing of the DBI flag signals ‘DFLAG<0:3>’, inverts the data according to the DBI flag signals ‘DFLAG<0:3>’, and outputs the data.
The MULTIPLEXING/PIPE LATCH unit 3-3 performs a multiplexing and pipe latching operation on the inverted data.
As described above, in the semiconductor integrated circuit disclosed by the prior art in FIGS. 1 and 2, the data bus inversion is performed in each of the first to eighth data output units 3 to 10 in accordance with the DBI flag signals ‘DFLAG<0:3>’ generated by the DBI flag generating unit 2.
Accordingly, the control/delay circuit unit 3-1 and the inversion circuit unit 3-2 are required in each of the first to eighth data output units 3 to 10, wherein the IC layout area increases. That is, the first to eighth data output units 3 to 10 are disposed in the area where the circuits related to data input are also disposed, which makes designing the semiconductor integrated circuit difficult.
Further, timing of the data and timing of the DBI flag signal need to be matched with respect to each of the first to eighth data output units 3 to 10. By having the control/delay circuit unit 3-1 and the inversion circuit unit 3-2 required in each of the first to eighth data output units 3 to 10, the ability to design timing circuits to perform data input/output control is made more difficult. Consequently, the input/output timings of all of the pads may not be matched with respect to the timing of the data and the DBI flag signal.